Non-volatile memories are commonly used in several applications when the data stored in the memory need to be preserved even in absence of a power supply. Within the class of non-volatile memories, electrically programmable (and erasable) memories, such as flash memories, have become very popular in applications in which the data to be stored are not immutable (as it might be case of, e.g., a consolidated code for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored. Examples of such applications include memory cards of the type used for example in digital cameras.
Typically, the memory includes an arrangement of memory cells, disposed for example in rows and columns, so as to form a matrix. Depending on the way the memory cells in the matrix are interconnected, a so-called NAND architecture for the flash memories can be identified. Roughly speaking in a NAND architecture groups of memory cells of a same matrix column are serially interconnected so as to form respective strings, which strings are then connected in parallel to each other to a same bit line. NAND flash memories are compact (a low number of contacts in the matrix are required), and they are suited for applications such as file storage.
In the NAND architecture, the memory space is partitioned into a plurality of memory blocks or sectors, each memory block including a plurality of memory cell strings connected between two common select lines. Each row of memory cells is in turn connected to a respective word line and then each memory block is associated with a number of word lines equal to the number of memory cells in one string. In order to access a memory cell for a read or a write operation, or even for testing it, the corresponding word line and bit line have to be properly biased together with the two select lines of the respective memory block.
For accessing a desired memory location an external device provides an address to the NAND memory; a first address portion corresponds to the memory block and a second address portion corresponds to the word line containing the addressed memory location. The NAND memory includes a row decoder receiving the address and, in turn, the row decoder includes a block decoder for addressing the desired memory block in response to the decoding of the block address portion and a word line decoder for properly biasing the word lines and the two select lines in response to the decoding of the word line address portion.
Typically, for saving occupied semiconductor area a word line decoder is connected to two global select lines and to global word lines, in turn connectable to the two select lines and to the word lines of the selected block, respectively, by means of respective pass transistors controlled by the block decoder. In detail, the block decoder allows connecting the two select lines and the word lines of the desired memory block to the global lines properly biased by the word line decoder. Then, the word line decoder comprises one driver for each global line instead of one driver for each line controlling the access to the memory cells. In addition, for each memory block the row decoder usually includes control units, receiving decoding signals corresponding to the block address portion and, accordingly, providing signals taking voltage values suitable for the required operations on the NAND memory, such as the value of a supply voltage or the value of a voltage bootstrapped with respect to the supply voltage. In detail, the gate terminals of the pass transistors corresponding to each memory block are connected to a common node biased by a respective control unit. Such a structure permits implementation of a row decoder occupying a relatively small area in accordance to the compact architecture of the NAND memories.
In solutions known in the art, the selection of the desired location includes precharging the common nodes connected to the gate terminals of all the pass transistors at the bootstrapped voltage; after the precharge, the common nodes corresponding to the memory blocks not addressed are discharged to a voltage suitable to keep the word lines and the select lines disconnected from the word line decoder, i.e. to keep the pass transistors switched off. Instead, the common node corresponding to the addressed memory block kept floating at the bootstrapped voltage for the duration of the required operation.
Inevitably, the common node left floating in turn tends to discharge from the bootstrapped voltage because of leakages and, accordingly, the duration of an operation on the NAND memory has to be limited to a relatively short time. This is not a problem for operations, such as a read or a write operation, having typical durations about from ten to thirty microseconds, but there are operations, such as operations in test mode, which can require periods of the order of tens of milliseconds.
An example of operation in test mode is the so-called Direct Memory Access (DMA); in a DMA phase the bit lines are directly connected to respective input/output pads of the memory device biased to a suitable voltage, while the voltage at the word lines is varied by the word line decoder. Particularly, a memory cell is accessed in DMA for sensing the current sunk thereby, by means of an external testing device connected to the corresponding input/output pad. Accordingly, the DMA permits to identify defective memory cells and, in addition to characterize the memory cells, for example to obtain a threshold voltage distribution.
As a consequence, a discharge of the floating common node corresponding to the selected block makes unreliable, if not unfeasible, the current sensing in DMA mode because of the relatively long duration thereof.
In view of the state of the art outlined in the foregoing, one of the problems that the Applicant has faced has been how to provide a row decoder for NAND memories which permits performance in a reliable way, in particular without impacting on the compactness of the NAND memories, operations necessitating relatively long times, during which the word lines and the select lines of the selected block should be kept driven by the row decoder, particularly operations requiring times longer than typical times required by read and write operations, such as in a DMA operation.